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Altera

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198 open roles · newest 50 below

  • FPGA Design Applications Engineer

    San Francisco

  • Software Engineer - Intern

    Toronto

  • Software Enabling and Optimization Engineer

    San Francisco

  • FPGA IP Design Engineer - Intern

    Toronto

  • Senior Financial Analyst

    San Francisco

  • Senior Manager, Global Consolidation

    San Francisco

  • Timing Engineer

    San Francisco

  • High Level Synthesis (HLS) Compiler Engineer (Intern))

    Marlow

  • Undergrad Intern Technical

    Haifa

  • Principal/Senior Principal Engineer - Physical Design Implementation and Signoff Methodology

    San Francisco

  • Cyber Offense, SOC, and IR Lead

    San Francisco

  • Staff Application Engineer

    San Francisco

  • DFT Design Engineer

    Jerusalem

  • Senior DFT Design Engineer

    San Francisco

  • Analog Layout Design Engineer

    Bengaluru

  • Director, Physical Design

    San Francisco

  • Identity and Data Cyber Defense Lead

    San Francisco

  • Endpoint and Data Security Engineer

    San Francisco

  • Security Operations Center Lead

    San Francisco

  • Full Chip Timing Modeling and Integration Engineer

    San Francisco

  • Senior Director, Silicon Architecture and Design Engineering (Ethernet)

    San Francisco

  • Senior Financial Analyst - Engineering Finance

    San Francisco

  • Commodity Manager

    San Francisco

  • Physical AI Solutions Architect

    Marlow

  • HW and DSP Graduate Intern

    Bengaluru

  • Senior MTS - Product Development Engineer

    San Francisco

  • AI Architect, Agentic AI for Chip Design & EDA

    San Francisco

  • Senior FPGA IP Solutions Engineer – Robotics Technology

    Marlow

  • Senior Technical Program Manager

    San Francisco

  • MTS - Product Development Engineer

    San Francisco

  • Program Manager, Government and Industry

    San Francisco

  • Senior Security Analyst: Assurance and Global Compliance

    San Francisco

  • Functional Safety Architect

    San Francisco

  • Lead Technical Program Manager

    San Francisco

  • Product Architectural Model Development Leader

    San Francisco

  • DevSecOps and AI/Automation Engineer

    San Francisco

  • Senior FPGA Silicon Validation Engineer

    San Francisco

  • Infrastructure Cyber Defense Leader

    San Francisco

  • Senior Director, Business Development – Physical AI, Robotics & Drones (Europe & APAC)

    Haifa

  • Senior Product Development Engineer

    San Francisco

  • Workday Functional Solutions Architect

    San Francisco

  • Senior Principal Engineer

    San FranciscoRemote

  • Senior Debug Verification Engineer

    San Francisco

  • AIOPs Observability/SRE Lead

    San Francisco

  • AI Engineer – Cloud Software & AI Platforms - Contract

    San Francisco

  • CPU Design Engineer

    San Francisco

  • Lead Product Planner

    San Francisco

  • Senior QMS Engineer

    San Francisco

  • Digital Design Verification Engineer

    San FranciscoRemote

  • Business Development Manager – Embedded

    Marlow